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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adf4206/adf4207/adf4208 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 dual rf pll frequency synthesizers functional block diagram oscillator clock data le 22-bit data register muxout adf4206/adf4207/adf4208 cp rf1 cp rf2 phase comparator output mux 14-bit rf2 r-counter osc in rf1 in a rf1 in b v dd 1v dd 2v p 1v p 2 agnd rf1 dgnd rf1 dgnd rf2 agnd rf2 sdout rf2 prescaler rf2 in a 11-bit rf2 b-counter 6-bit rf2 a-counter rf2 in b osc out n = bp + a charge pump rf2 lock detect 14-bit rf1 r-counter rf1 prescaler 11-bit rf1 b-counter 6-bit rf1 a-counter n = bp + a rf1 lock detect phase comparator charge pump features adf4206: 550 mhz/550 mhz adf4207: 1.1 ghz/1.1 ghz adf4208: 2.0 ghz/1.1 ghz 2.7 v to 5.5 v power supply selectable charge pump supply (vp) allows extended tuning voltage in 3 v systems selectable charge pump currents on-chip oscillator circuit selectable dual modulus prescaler rf2: 32/33 or 64/65 rf1: 32/33 or 64/65 3-wire serial interface power-down mode applications wireless handsets (gsm, pcs, dcs, cdma, wcdma) base stations for wireless radio (gsm, pcs, dcs, cdma, wcdma) wireless lans communications test equipment catv equipment general description the adf4206 family of dual frequency synthesizers can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. each synthesizer consists of a low-noise digital pfd (phase frequency detector), a precision charge pump, a programmable reference divider, programmable a and b counters and a dual- modulus prescaler (p/p + 1). the a (6-bit) and b (11-bit) counters, in conjunction with the dual modulus prescaler (p/p + 1), implement an n divider (n = bp + a). in addition, the 14-bit reference counter (r counter), allows selectable refin frequen- cies at the pfd input. the on-chip oscillator circuitry allows the reference input to be derived from crystal oscillators. a complete pll (phase-locked loop) can be implemented if the synthesizers are used with an external loop ?ter and vcos (voltage controlled oscillators). control of all the on-chip registers is via a simple 3-wire interface. the devices operate with a power supply ranging from 2.7 v to 5.5 v and can be powered down when not in use.
rev. 0 C2C adf4206/adf4207/adf4208?pecifications 1 (v dd 1 = v dd 2 = 3 v 10%, 5 v 10%; v dd 1, v dd 2 v p 1, v p 2 6.0 v; agnd rf1 = dgnd rf1 = agnd rf2 = dgnd rf2 = 0 v; t a = t min to t max unless otherwise noted, dbm referred to 50 .) parameter b version b chips 2 unit test conditions/comments rf/if characteristics (3 v) see figure 2 for input circuit. rf1 input frequency (rf1 in ) use a square wave for frequencies lower than f min . adf4206 0.05/0.55 0.05/0.55 ghz min/max adf4207 0.08/1.1 0.08/1.1 ghz min/max adf4208 0.08/2.0 0.08/2.0 ghz min/max rf input sensitivity ?5/+4 ?5/+4 dbm min/max if input frequency (rf2 in ) adf4206 0.05/0.55 0.05/0.55 ghz min/max adf4207/adf4208 0.08/1.1 0.08/1.1 ghz min/max if input sensitivity ?5/+4 ?5/+4 dbm min/max maximum allowable prescaler output 165 165 mhz max frequency 3 rf characteristics (5 v) rf1 input frequency (rf1 in ) use a square wave for frequencies lower than f min . adf4206 0.05/0.55 0.05/0.55 ghz min/max adf4207 0.08/1.1 0.08/1.1 ghz min/max adf4208 0.08/2.0 0.08/2.0 ghz min/max rf input sensitivity ?0/+4 ?0/+4 dbm min/max if input frequency (rf2 in ) mhz min/max adf4206 0.05/0.55 0.05/0.55 ghz min/max adf4207/adf4208 0.08/1.1 0.08/1.1 ghz min/max if input sensitivity ?0/+4 ?0/+4 dbm min/max maximum allowable prescaler output 200 200 mhz max frequency 3 refin characteristics refin input frequency 5/40 5/40 mhz min/max for f < 5 mhz use square wave 0 to v dd refin input sensitivity 4 ? ? dbm min ac-coupled. when dc-coupled, 0 to v dd max (cmos-compatible) refin input capacitance 10 10 pf max refin input current 100 100 a max phase detector phase detector frequency 5 55 55 mhz max charge pump i cp sink/source high value 5 5 ma typ low value 1.25 1.25 ma typ absolute accuracy 2.5 2.5 % typ i cp three-state leakage current 1 1 na typ logic inputs v inh , input high voltage 0.8 v dd 0.8 v dd v min v inl , input low voltage 0.2 v dd 0.2 v dd v max i inh /i inl , input current 1 1 a max c in , input capacitance 10 10 pf max logic outputs v oh , output high voltage v dd ?0.4 v dd ?0.4 v min i oh = 500 a v ol , output low voltage 0.4 0.4 v max i ol = 500 a power supplies v dd 1 2.7/5.5 2.7/5.5 v min/v max v dd 2v dd 1v dd 1 v p v dd 1/6.0 v dd 1/6.0 v min/v max v dd 1, v dd 2 v p 1, v p 2 6.0 v i dd (i dd 1 + i dd 2) 6 adf4206 14 14 ma max 9.5 ma typical at v dd = 3 v, t a = 25 c adf4207 16.5 16.5 ma max 11 ma typical at v dd = 3 v, t a = 25 c adf4208 21 21 ma max 14 ma typical at v dd = 3 v, t a = 25 c i dd 1 adf4206 8 8 ma max 5.5 ma typical at v dd = 3 v, t a = 25 c adf4207 9 9 ma max 6 ma typical at v dd = 3 v, t a = 25 c adf4208 14 14 ma max 9 ma typical at v dd = 3 v, t a = 25 c i dd 2 adf4206 7.5 7.5 ma max 5 ma typical at v dd = 3 v, t a = 25 c adf4207 8.5 8.5 ma max 5.5 ma typical at v dd = 3 v, t a = 25 c adf4208 9 9 ma max 5.5 ma typical at v dd = 3 v, t a = 25 c i p (i p 1 + i p 2) 1 1 ma max t a = 25 c low-power sleep mode 0.5 0.5 a typ
rev. 0 C3C adf4206/adf4207/adf4208 parameter b version b chips 2 unit test conditions/comments noise characteristics phase noise floor (rf1) 7 adf4206 ?69 ?69 dbc/hz typ @ 25 khz pfd frequency adf4207 ?71 ?71 dbc/hz typ @ 25 khz pfd frequency adf4208 ?73 ?73 dbc/hz typ @ 25 khz pfd frequency adf4206 ?60 ?60 dbc/hz typ @ 200 khz pfd frequency adf4207 ?62 ?62 dbc/hz typ @ 200 khz pfd frequency adf4208 ?64 ?64 dbc/hz typ @ 200 khz pfd frequency phase noise performance 8 @ vco output adf4206 (rf1, rf2) ?2 ?2 dbc/hz typ @ 540 mhz output, 200 khz at pfd adf4207 (rf1, rf2) ?0 ?0 dbc/hz typ @ 900 mhz output, 200 khz at pfd adf4207 (rf1, rf2) 9 ?1 ?1 dbc/hz typ @ 836 mhz, 30 khz at pfd adf4208 (rf1) ?5 ?5 dbc/hz typ @ 1750 mhz output, 200 khz at pfd adf4208 (rf1) ?1 ?1 dbc/hz typ @ 900 mhz output, 200 khz at pfd adf4208 (rf1) 10 ?6 ?6 dbc/hz typ @ 1750 mhz output, 200 khz at pfd adf4208 (rf2) ?9 ?9 dbc/hz typ @ 900 mhz output, 200 khz at pfd spurious signals rf1, rf2 (20 khz loop b/w) ?0/?4 ?0/?4 db typ @ 200 khz/400 khz and 200 khz pfd rf1, rf2 (1 khz loop b/w) ?5/?3 ?5/?3 db typ @10 khz/20 khz and 10 khz pfd notes 1 operating temperature range is as follows: b version: ?0 c to +85 c. 2 the b chip speci?ations are given as typical values. 3 this is the maximum operating frequency of the cmos counters. the prescaler value should be chosen to ensure that the rf input is divided down to a frequency that is less than this value. 4 v dd 1 = v dd 2 = 3 v; for v dd 1 = v dd 2 = 5 v, use cmos-compatible levels. 5 guaranteed by design. sample tested to ensure compliance. 6 typical values apply for v dd = 3 v; p = 32; rf1 in 1/rf2 in 2 for adf4206 = 540 mhz; rf1 in 1/rf2 in 2 for adf4207 = 900 mhz; rf1 in 1/rf2 in 2 for adf4208 = 900 mhz. 7 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 logn (where n is the n divider value). 8 the phase noise is measured at a 1 khz unless otherwise noted. the phase noise is measured with the eval-adf4206/adf4207eb or t he eval-ad4208eb evaluation board and the hp8562e spectrum analyzer. the spectrum analyzer provides the refin for the synthesizer (f refout = 10 mhz @ 0 dbm). 9 f refin = 10 mhz; f pfd = 30 khz; offset frequency = 300 hz; f rf/if = 836 mhz; n = 27866; loop b/w = 3 khz. 10 f refin = 10 mhz; f pfd = 10 khz; offset frequency = 200 hz; f rf = 1750 mhz; n = 175000; loop b/w = 1 khz. speci?ations subject to change without notice.
rev. 0 adf4206/adf4207/adf4208 C4C timing characteristics limit at t min to t max parameter (b version) unit test conditions/comments t 1 10 ns min data to clock setup time t 2 10 ns min data to clock hold time t 3 25 ns min clock high duration t 4 25 ns min clock low duration t 5 10 ns min clock to le setup time t 6 20 ns min le pulsewidth notes guaranteed by design but not production tested. speci?ation subject to change without notice. (v dd 1 = v dd 2 = 3 v 10%, 5 v 10%; v dd 1, v dd 2 v p 1, v p 2 6.0 v; agnd rf1 = dgnd rf1 = agnd rf2 = dgnd rf2 = 0 v; t a = t min to t max unless otherwise noted, dbm referred to 50 .) db0 (lsb) (control bit c1) clock db21 (msb) db20 db2 data le le t 3 t 4 t 2 t 5 t 1 t 6 db1 (control bit c2) figure 1. timing diagram absolute maximum ratings 1, 2 (t a = 25 c unless otherwise noted.) v dd 1 to gnd 3 . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v dd 1 to v dd 2 . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v v p 1, v p 2 to gnd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v v p 1, v p 2 to v dd 1 . . . . . . . . . . . . . . . . . . . . ?.3 v to +5.5 v digital i/o voltage to gnd . . . . . . ?.3 v to dv dd + 0.3 v analog i/o voltage to gnd . . . . . . . . . ?.3 v to v p + 0.3 v osc in , osc out , rf1 in (a, b), rf2 in (a, b) to gnd . . . . . . . . . . . . ?.3 v to v dd + 0.3 v rf in a to rf in b (rf1, rf2) . . . . . . . . . . . . . . . . . . 320 mv operating temperature range industrial (b version) . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . 150 c tssop ja thermal impedance . . . . . . . . . . . . . 150.4 c/w csp ja (paddle soldered) . . . . . . . . . . . . . . . . . . . 122 c/w csp ja (paddle not soldered) . . . . . . . . . . . . . . . . 216 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 this device is a high-performance rf integrated circuit with an esd rating of < 2 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. 3 gnd = agnd = dgnd = 0 v. transistor count 11749 (cmos) and 522 (bipolar). ordering guide model temperature range package description package option * ADF4206BRU ?0 c to +85 c thin shrink small outline package (tssop) ru-16 adf4207bru ?0 c to +85 c thin shrink small outline package (tssop) ru-16 adf4208bru ?0 c to +85 c thin shrink small outline package (tssop) ru-20 * contact the factory for chip availability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adf4206/adf4207/adf4208 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 adf4206/adf4207/adf4208 C5C pin function descriptions mnemonic pin adf4206/ no. adf4207 adf4208 function 1v dd 1v dd 1 positive power supply for the rf1 section. a 0.1 f capacitor should be connected between this pin and the rf1 ground pin, dgnd rf1 . v dd 1 should have a value of between 2.7 v and 5.5 v. v dd 1 must have the same potential as v dd 2. 2v p 1v p 1 power supply for the rf1 charge pump. this should be greater than or equal to v dd . 3cp rf1 cp rf1 output from the rf1 charge pump. this is normally connected to a loop filter which, in turn, drives the input to an external vco. 4 dgnd rf1 dgnd rf1 ground pin for the rf1 digital circuitry. 5 rf1 in rf1 in a input to the rf1 prescaler. this low-level input signal is normally taken from the rf1 vco. 6 osc in rf in b complementary input to the rf1 prescaler of the adf4208. this point should be decou pled to the ground plane with a small bypass capacitor. 7osc out agnd rf1 ground pin for the rf1 analog circuitry. 8 muxout osc in oscillator input. it has a v dd /2 threshold and can be driven from an external cmos or ttl logic gate. 9 clk osc out oscillator output. 10 data muxout this multiplexer output allows either the if/rf lock detect, the scaled rf, or the scaled reference frequency to be accessed externally. see table v. 11 le clk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 22-bit shift register on the clk rising edge. this input is a high impedance cmos input. 12 rf2 in data serial data input. the serial data is loaded msb ?st with the two lsbs being the control bits. this input is a high impedance cmos input. 13 dgnd rf2 le load enable, cmos input. when le goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. 14 cp rf2 agnd rf2 ground pin for the rf2 analog circuitry. 15 v p 2 rf2 in b complementary input to the rf2 prescaler. this point should be decoupled to the ground plane with a small bypass capacitor. 16 v dd 2 rf2 in a input to the rf2 prescaler. this low-level input signal is normally ac-coupled to the external vco. 17 dgnd rf2 ground pin for the rf2, digital, interface, and control circuitry. 18 cp rf2 output from the rf2 charge pump. this is normally connected to a loop filter that drives the input to an external vco. 19 v p 2 power supply for the rf2 charge pump. this should be greater than or equal to v dd . 20 v dd 2 positive power supply for the rf2, interface, and oscillator sections. a 0.1 f capacitor should be connected between this pin and the rf2 ground pin, dgnd rf2 . v dd 2 should have a value between 2.7 v and 5.5 v. v dd 2 must have the same potential as v dd 1. pin configurations tssop top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 v dd 1 v p 1 cp rf1 dgnd rf1 rf1 i n osc in osc out muxout v dd 2 v p 2 cp rf2 dgnd rf2 rf2 in le data clk adf4206/ adf4207 tssop top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 adf4208 v dd 1 v p 1 cp rf1 dgnd rf1 rf1 i n a osc in osc out muxout v dd 2 v p 2 cp rf2 agnd rf2 le data clk rf1 i n b agnd rf1 rf2 i n b rf2 i n a dgnd rf2
rev. 0 adf4206/adf4207/adf4208 C6C typical performance characteristics freq-unit param-type data-format keyword impedance ?ohms ghz s ma r 50 freq mags11 angs11 1.35 0.816886959 51.80711782 1.45 0.825983016 56.20373378 1.55 0.791737125 61.21554647 1.65 0.770543186 61.88187496 1.75 0.793897072 65.39516615 1.85 0.745765233 69.24884474 1.95 0.7517547 71.21608147 2.05 0.745594889 75.93169947 2.15 0.713387801 78.8391674 2.25 0.711578577 81.71934806 2.35 0.698487131 85.49067481 2.45 0.669871818 88.41958754 2.55 0.668353367 91.70921678 freq mags11 angs11 0.0 0.957111193 3.130429321 0.15 0.963546793 6.686426265 0.25 0.953621785 11.19913586 0.35 0.953757706 15.35637483 0.45 0.929831379 20.3793432 0.55 0.908459709 22.69144845 0.65 0.897303634 27.07001443 0.75 0.876862863 31.32240763 0.85 0.849338092 33.68058163 0.95 0.858403269 38.57674885 1.05 0.841888714 41.48606772 1.15 0.840354983 45.97597958 1.25 0.822165839 49.19163116 tpc 1. s-parameter data for the ad4208 rf1 input (up to 2.5 ghz) 0 5 10 15 20 25 30 35 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v dd = 5v v p = 5v t a = +85 c t a = +25 c t a = 40 c rf input power dbm rf input sensitivity ghz tpc 2. input sensitivity for the adf4208 (rf1) frequency hz 2k 2k 1k 900m 1k output power db 0 90 80 70 60 30 20 50 40 10 100 90.5dbc/hz reference level = 4.2dbm v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 10hz video bandwidth = 10hz sweep = 1.9 seconds averages = 19 tpc 3. adf4208 rf1 phase noise (900 mhz, 200 khz, 20 khz) frequency hz 400k 400k 200k 900m 200k output power db 0 90 80 70 60 30 20 50 40 10 100 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 20khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 30 90.2dbc/hz reference level = 4.2dbm tpc 4. a df4208 rf1 reference spurs (900 mhz, 200 khz, 20 khz) frequency offset from 900mhz carrier 40 100hz 1mhz phase noise dbc/hz 50 60 70 80 90 100 110 120 130 140 1khz 10khz 100khz 0.52 rms 10db/division r l = 40dbc/hz rms noise = 0.52 tpc 5. adf4208 rf1 integrated phase noise (900 mhz, 200 khz, 20 khz) frequency offset from 900mhz carrier 40 100hz 1mhz phase noise dbc/hz 50 60 70 80 90 100 110 120 130 140 1khz 10khz 100khz 0.62 rms 10db/division r l = 40dbc/hz rms noise = 0.62 tpc 6. adf4208 rf1 integrated phase noise (900 mhz, 200 khz, 35 khz)
rev. 0 adf4206/adf4207/adf4208 C7C frequency hz 400k 400k 200k 900m 200k output power db 0 90 80 70 60 30 20 50 40 10 100 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 200khz loop bandwidth = 35khz res. bandwidth = 1khz video bandwidth = 1khz sweep = 2.5 seconds averages = 30 89.3dbc reference level = 4.2dbm tpc 7. adf4208 rf1 reference spurs (900 mhz, 200 khz, 35 khz) frequency hz 400 400 200 1750m 200 output power db 0 90 80 70 60 30 20 50 40 10 100 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 30khz loop bandwidth = 3khz res. bandwidth = 10khz video bandwidth = 10khz sweep = 477ms averages = 10 75.2dbc/hz reference level = 8.0dbm tpc 8. adf4208 rf1 phase noise (1750 mhz, 30 khz, 3 khz) frequency offset from 1750mhz carrier 40 100hz 1mhz phase noise dbc/hz 50 60 70 80 90 100 110 120 130 140 1khz 10khz 100khz 1.6 rms 10db/division r l = 40dbc/hz tpc 9. adf4208 rf1 integrated phase noise (1750 mhz, 30 khz, 3 khz) frequency hz 80k 400k 200k 1750m 40k output power db 0 90 80 70 60 30 20 50 40 10 100 v dd = 3v, v p = 5v i cp = 5ma pfd frequency = 30khz loop bandwidth = 3khz res. bandwidth = 3hz video bandwidth = 3hz sweep = 255 seconds positive peak detect mode 79.6dbc reference level = 5.7dbm tpc 10. a df4208 rf1 reference spurs (1750 mhz, 30 khz, 3 khz) 120 130 140 150 160 170 180 1 10 100 1000 10000 phase noise dbc/hz phase detector frequency khz v dd = 3v v p = 5v adf4206 adf4207 adf4208 (,- '' &%#0 &' , ! ,& &
: temperature c 100 40 0 20 40 60 80 100 phase noise dbc/hz 70 80 90 60 20 v dd = 3v v p = 3v (,-'# &%#0&',! (

1674#84#845
rev. 0 adf4206/adf4207/adf4208 C8C temperature c 100 40 0 20 40 60 80 100 first reference spur dbc 70 80 90 60 20 v dd = 3v v p = 5v tpc 13. adf4208 rf1 reference spurs vs. temperature (900 mhz, 200 khz, 20 khz) tuning voltage v 5 0234 105 first reference spur dbc 75 85 95 5 1 v dd = 3v v p = 5v 65 35 45 55 15 25 tpc 14. adf4208 rf1 reference spurs vs. v tune (900 mhz, 200 khz, 20 khz) 120 130 140 150 160 170 180 1 10 100 1000 10000 phase noise dbc/hz phase detector frequency khz v dd = 3v v p = 5v adf4206 adf4207 adf4208 tpc 15. adf4208 rf2 phase noise vs. pfd frequency prescaler output frequency mhz 200 0 150 0 di dd ma v dd = 3v v p = 3v 3.0 2.5 1.5 1.0 2.0 0.5 100 50 tpc 16 di dd vs. prescaler output frequency (all models, rf1 and rf2) prescaler value 10 9 0 32/33 64/65 6 3 2 1 8 7 4 5 ai dd ma adf4206 adf4207 adf4208 tpc 17. adf4206/adf4207/adf4208 ai dd vs. prescaler value (rfi)
rev. 0 adf4206/adf4207/adf4208 C9C circuit description reference input section the reference input stage is shown in figure 2. sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed and sw1 and sw2 are opened. typical recommended external components are shown in figure 2. 30pf osc in osc out to r counter buffer power-down control sw1 nc nc sw2 100k sw3 no 18k 30pf figure 2. rf input stage rf input stage the rf input stage is shown in figure 3. it is followed by a 2-stage limiting ampli?r to generate the cml clock levels needed for the prescaler. rf in a av dd bias generator 1.6v 2k agnd 2k rf in b figure 3. rf input stage prescaler the dual modulus prescaler (p/p + 1), along with the a and b counters, enables the large division ratio, n, to be realized (n = bp + a). this prescaler, operating at cml levels, takes the clock from the rf input stage and divides it down to a man- ageable frequency for the cmos a and b counters. it is based on a synchronous 4/5 core. the prescaler is selectable. both rf1 and rf2 can be set to either 32/33 or 64/65. db20 of the ab counter latch selects the value. see tables iv and vi. a and b counters the a and b cmos counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the pll feed- back counter. the devices are guaranteed to work when the prescaler output is 200 mhz or less. pulse swallow function the a and b counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the equation for the vco frequency is as follows: f vco = [( p b ) + a ] f refin / r f vco = output frequency of external voltage controlled oscillator (vco). p = preset modulus of dual modulus prescaler (32/33, 64/65). b = preset divide ratio of binary 11-bit counter (1 to 2047). a = preset divide ratio of binary 6-bit a counter (0 to 63). f refin = output frequency of the external reference frequency oscillator. r = preset divide ratio of binary 14-bit programmable reference counter (1 to 16383). r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. prescaler p/p + 1 modulus control from rf input stage load n = bp + a n divider load to pfd 11-bit b counter 6-bit a counter figure 4. a and b counters phase frequency detector (pfd) and charge pump the pfd takes inputs from the r counter and n counter (n = bp + a) and produces an output proportional to the phase and frequency difference between them. figure 5 is a simpli?d schematic.
rev. 0 adf4206/adf4207/adf4208 C10C delay element u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 r divider n divider cp output r divider n divider cp cpgnd v p figure 5. pfd simpli?ed schematic and timing (in lock) the pfd includes a delay element which sets the width of the antibacklash phase. the typical value for this is in the adf4206 family is 3 ns. the pulse ensures that there is no deadzone in the pfd transfer function and minimizes phase noise and refer- ence spurs. muxout and lock detect the output multiplexer on the adf4206 family allows the user to access various internal points on the chip. the state of muxout is controlled by p3, p4, p11, and p12. see tables iii and v. figure 6 shows the muxout section in block diagram form. control mux dv dd muxout dgnd rf2 analog lock detect rf2 r counter output rf2 n counter output rf2/rf1 analog lock detect rf1 r counter output rf1 n counter output rf1 analog lock detect figure 6. muxout circuit lock detect muxout can be programmed for analog lock detect. the n-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k ? nominal. when lock has been detected it is high with narrow low-going pulses. input shift register the functional block diagram for the adf4206 family is shown on page 1. the main blocks include a 22-bit input shift register, a 14-bit r counter, and an 17-bit n counter, comprising a 6-bit a counter and an 11-bit b counter. data is clocked into the 22-bit shift register on each rising edge of clk. the data is clocked in msb ?st. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. these are the two lsbs db1, db0, as shown in the timing diagram of figure 1. the truth table for these bits is shown in table i. table i. c2, c1 truth table control bits c2 c1 data latch 0 0 rf2 r counter 0 1 rf2 ab counter (and prescaler select) 1 0 rf1 r counter 1 1 rf1 ab counter (and prescaler select)
rev. 0 adf4206/adf4207/adf4208 C11C table ii. adf4206 family latch summary db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p1 p5 p2 p4 control bits 14-bit reference counter, r db21 rf2 pd polarity rf2 cp gain three-state cp rf2 rf2 lock detect p3 not used rf2 reference counter latch rf2 f o db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) a1 a2 a3 a4 a5 a6 b11 p6 control bits 11-bit b counter db21 rf2 prescaler p7 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 6-bit a counter rf2 power-down rf2 ab counter latch not used db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p9 p13 control bits 14-bit reference counter, r db21 rf1 pd polarity three-state cp rf1 rf1 lock detect rf1 f o p12 p10 p11 not used rf1 cp gain rf1 reference counter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (1) a1 a2 a3 a4 a5 a6 b11 control bits 11-bit b counter db21 rf1 ab counter latch b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 p16 p14 6-bit a counter rf1 power-down rf1 prescaler not used
rev. 0 adf4206/adf4207/adf4208 C12C table iii. rf2 reference counter latch map r14 r13 r12 .......... r3 r2 r1 divide ratio 0 0 0 .......... 0011 0 0 0 .......... 0102 0 0 0 .......... 0113 0 0 0 .......... 1004 . . . .......... .... . . . .......... .... . . . .......... .... 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 p1 pd polarity 0 negative 1 positive p12 p11 from rf1 r latch p4 p3 muxout 0000 logic low state 0001 rf2 analog lock detect 0 x 1 0 rf2 reference divider output 0 x 1 1 rf2 n divider output 0100 rf1 analog lock detect 0101 rf1/rf2 analog lock detect 1 x 0 0 rf1 reference divider 1 x 0 1 rf1 n divider 1010 fast lock output switch on and connected to muxout 1011 rf2 counter reset 1110 rf1 counter reset 1111 rf2 and rf1 counter reset db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p1 p2 p3 p4 control bits 14-bit reference counter, r db21 rf2 pd polarity three-state cp rf2 rf2 lock detect rf2 f o rf2 reference counter latch p5 i cp 0 1.25 ma 1 4.375 ma p5 rf2 cp gain p2 charge pump output 0 normal 1 three-state
rev. 0 adf4206/adf4207/adf4208 C13C table iv. rf2 ab counter latch map b11 b10 b9 b3 b2 b1 b counter divide ratio 000..........000not al lowed 000..........001not al lowed 000..........010not al lowed 000..........0113 ................. ................. ................. 111..........100 2044 111..........101 2045 111..........110 2046 111..........111 2047 a counter a6 a5 a4 a3 a2 a1 divide ratio xx00000 xx00011 xx00102 xx00113 ...... ...... ...... xx111014 xx111115 n = bp + a, p is prescaler value set by p6. b must be greater than or equal to a. to ensure continuously adjacent values of nx f ref , n min is (p 2 p). p7 rf2 section 0 normal operation 1 power-down db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) a1 a2 a3 a4 a5 a6 b11 p6 control bits 11-bit b counter db21 rf2 ab counter latch rf2 power- down rf2 prescaler p7 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 6-bit a counter p6 rf2 prescaler 0 64/65 1 32/33
rev. 0 adf4206/adf4207/adf4208 C14C table v. rf1 reference counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 p9 p13 control bits 14-bit reference counter, r db21 rf1 pd polarity three-state cp rf1 rf1 lock detect rf1 f o rf1 reference counter latch p10 p11 r14 r13 r12 .......... r3 r2 r1 divide ratio 0 0 0 .......... 0011 0 0 0 .......... 0102 0 0 0 .......... 0113 0 0 0 .......... 1004 . . . .......... .... . . . .......... .... . . . .......... .... 1 1 1 .......... 1 0 0 16380 1 1 1 .......... 1 0 1 16381 1 1 1 .......... 1 1 0 16382 1 1 1 .......... 1 1 1 16383 p9 pd polarity 0 negative 1 positive p13 i cp 0 1.25 ma 1 4.375 ma p4 p3 p12 p11 from rf2 r latch muxout 0000 logic low state 0001 rf2 analog lock detect 0 x 1 0 rf2 reference divider output 0 x 1 1 rf2 n divider output 0100 rf1 analog lock detect 0101 rf1/rf2 analog lock detect 1 x 0 0 rf1 reference divider 1 x 0 1 rf1 n divider 1010 fast lock output switch on and connected to muxout 1011 rf2 counter reset 1110 rf1 counter reset 1111 rf2 and rf1 counter reset p12 rf1 cp gain p10 charge pump output 0 normal 1 three-state
rev. 0 adf4206/adf4207/adf4208 C15C table vi. rf1 ab counter latch map db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 db21 c2 (1) c1 (1) a1 a2 a3 a4 a5 a6 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 p14 p16 control bits 11-bit b counter rf1 power- down rf1 prescaler 6-bit a counter b11 b10 b9 b3 b2 b1 b counter divide ratio 000..........0011 000..........0102 000..........0113 000..........1003 ................. ................. ................. 1 1 1 .......... 1 0 0 2044 1 1 1 .......... 1 0 1 2045 1 1 1 .......... 1 1 0 2046 1 1 1 .......... 1 1 1 2047 a counter a6 a5 a4 a3 a2 a1 divide ratio 0000000 0000011 0000102 0000113 ...... ...... ...... 11111062 11111163 n = bp + a, p is prescaler value set by p6. b must be greater than or equal to a. for continuously adjacent values of n, n min is (p 2 p). p16 rf1 section 0 normal operation 1 power-down p14 rf1 prescaler 0 64/65 1 32/33 rf1 ab counter latch
rev. 0 adf4206/adf4207/adf4208 C16C program modes table iii and table v show how to set up the program modes in the adf420x family. the following should be noted: 1. rf2 and rf1 analog lock detect indicate when the pll is in lock. when the loop is locked and either rf2 or rf1 analog lock detect is selected, the muxout pin will show a logic high with narrow low-going pulses. when the r f2/rf1 analog lock detect is chosen, the locked condition is indi- cated only when both rf2 and rf1 loops are locked. 2. the rf2 counter reset mode resets the r and ab counters in the rf2 section and also puts the rf2 charge pump into three-s tate. the rf1 counter reset mode resets the r and ab counters in the rf1 section and also puts the rf1 charge pump into three-state. the rf2 and rf1 counter reset mode does both of the above. upon removal of the reset bits, the ab counter resumes count- ing in close alignment with the r counter (maximum error is one prescaler output cycle). 3. the fastlock mode uses muxout to switch a second loop ?ter damping resistor to ground during fastlock operation. activation of fastlock occurs whenever rf1 cp gain in the rf1 reference counter is set to one. power-down it is possible to program the adf420x family for either syn- chronous or asynchronous power-down on either the rf2 or rf1 side. synchronous rf2 power-down programming a ??to p7 of the adf420x family will initiate a power-down. if p2 of the adf420x family has been set to ? (normal operation), a synchronous power-down is conducted. the device will automatically put the charge pump into three- state and then complete the power-down. asynchronous rf2 power-down if p2 of the adf420x family has been set to ??(three-state the rf2 charge pump), and p7 is subsequently set to ?,?an asynchronous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the ??to the rf2 power-down bit (p7). synchronous rf1 power-down programming a ??to p16 of the adf420x family will initiate a power-down. if p10 of the adf420x family has been set to ??( normal operation), a synchronous power-down is conducted. the device will automatically put the charge pump into three- state and then complete the power-down. asynchronous rf1 power-down if p10 of the adf420x family has been set to ??(three-state the rf1 charge pump), and p16 is subsequently set to ?,?an asynchronous power-down is conducted. the device will go into power-down on the rising edge of le, which latches the ??to the rf1 power-down bit (p16). activation of either synchronous or asynchronous power-down forces the rf2/rf1 loop? r and n dividers to their load state conditions and the rf2/rf1 input section is debiased to a high im pedance state. the reference oscillator circuit is only disabled if both the rf2 and rf1 power-downs are set. the input register and latches remain active and are capable of loading and latching data during all the power-down modes. the rf2/rf1 section of the devices will return to normal pow- ered up operation immediately upon le latching a ??to the appropriate power-down bit. if section (rf2) programmable rf2 reference (r) counter if control bits (c2, c1) are (0, 0), the data is transferred from the input shift register to the 14-bit rf2 r counter. table iii shows the input shift register data format for the rf2 r counter and the divide ratios possible. rf2 phase detector polarity p1 sets the rf2 phase detector polarity. when the rf2 vco characteristics are positive, this should be set to ?.?when they are negative, it should be set to ?.?see table iii. rf2 charge pump three-state p2 puts the rf2 charge pump into three-state mode when pro- grammed to a ?.?it should be set to ??for normal operation. see table iii. rf2 program modes table iii and table v show how to set up the program modes in the adf420x family. rf2 charge pump currents bit p5 programs the current setting for the rf2 charge pump. see table iii. programmable rf2 ab counter if control bits (c2, c1) are (0, 1), the data in the input register is used to program the rf2 ab counter. the ab counter consists of a 6-bit swallow counter (a counter) and 11-bit programmable counter (b counter). table iv shows the input register data format for programming the rf2 ab counter and the divide ratios possible. rf2 prescaler value p6 in the rf2 ab counter latch sets the rf2 prescaler value. see table iv. rf2 power-down p7 in table iv is the power-down bit for the rf2 side.
rev. 0 adf4206/adf4207/adf4208 C17C rf section (rf1) programmable rf1 reference (r) counter if control bits (c2, c1) are (1, 0), the data is transferred from the input shift register to the 14 bit rf1 r counter. table v shows the input shift register data format for the rf1 r counter and the divide ratios possible. rf1 phase detector polarity p9 sets the rf1 phase detector polarity. when the rf1 vco characteristics are positive this should be set to ?.?when they are negative it should be set to ?.?see table v. rf1 charge pump three-state p10 puts the rf1 charge pump into three-state mode when programmed to a ?.?it should be set to ??for normal opera- tion. see table v. rf1 program modes table iii and table v show how to set up the program modes in the adf420x family. rf1 charge pump currents replaced with a p13 programs the current setting for the rf1 charge pump. see table v. programmable rf1 ab counter if control bits (c2, c1) are (1, 1), then the data in the input register is used to program the rf1 ab counter. the ab counter con sists of a 6-bit swallow counter (a counter) and 11-bit programmable counter (b counter). table vi shows the input register data format for programming the rf1 ab counter and the divide ratios possible. see table vi. rf1 prescaler value p14 in the rf1 a, b counter latch set the rf1 prescaler value. see table vi. rf1 power-down setting p16 in the rf1 ab counter high powers down rf1 side. rf fastlock the fastlock feature can improve the lock time of the pll. it increases charge pump current to a maximum for a period of time. fastlock of the adf420x family is activated by setting p13 in the reference counter high and setting the fastlock switch on using muxout. switching in an external resistor using muxout compensates the loop dynamics for the effect of increasing charge pump current. setting p13 low removes the pll from fastlock mode. osc out muxout adf4207 v p 2 v dd 2 v dd 1v p 1 cp rf1 rf2 in rf1 in osc in clk data le dgnd rf1 dgnd rf2 agnd rf1 agnd rf2 decoupling capacitors (22 f/10pf) on v dd , v p of the adf4207, and on v cc of the vcos have been omitted from the diagram to aid clarity. vco190-125t v cc cp rf2 v cc spi-compatible serial bus 100pf 18 18 18 100pf if out 100pf 51 30pf 10mhz 18k 1.3nf 13nf 2.7k 620pf 3.3k v p v dd v p 100pf 18 rf out 100pf 18 18 100pf 51 lock detect 30pf vco190-1068u figure 7. gsm handset receiver local oscillator using the adf4207
rev. 0 adf4206/adf4207/adf4208 C18C applications section local oscillator for gsm handset receiver figure 7 shows the adf4207 being used in a classic superhet- erodyne receiver to provide the required los (local oscillators). in this circuit, the reference input signal is applied to the circuit at osc in and is being generated by a 10 mhz crystal oscillator. this is a low -cost solution and for better performance over tem- perature, a tcxo (temperature controlled crystal oscillator) may be used instead. in order to have a channel spacing of 200 khz (the gsm stan- dard), the reference input must be divided by 50, using the on-chip reference counter. the rf output frequency range is 1050 mhz to 1086 mhz. loop ?ter component values are chosen so that the loop bandwidth is 20 khz. the synthesizer is set up for a charge pump current of 4.375 ma and the vco sensitivity is 15.6 mhz/v. osc out muxout adf4208 v p 2 v dd 2 v dd 1v p 1 cp rf1 rf2 in rf1 in osc in clk data le dgnd rf1 dgnd rf2 agnd rf1 agnd rf2 decoupling capacitors (22 f/10pf) on v dd , v p of the adf4208, and on v cc of the vcos have been omitted from the diagram to aid clarity. vco190-200t v cc cp rf2 v cc spi-compatible serial bus 100pf 18 18 18 100pf if out 100pf 51 30pf 10mhz 18k 1.3nf 13nf 2.7k 620pf 3.3k v p v dd v p 100pf 18 rf out 100pf 18 18 100pf 51 lock detect 30pf vco190-1750t figure 8. local oscillator for wcdma receiver using the adf4208 the if output is ?ed at 125 mhz. the if loop bandwidth is chosen to be 20 khz with a channel spacing of 200 khz. loop ?ter component values are chosen accordingly. local oscillator for wcdma receiver figure 8 shows the adf4208 being used to generate the local oscillator frequencies for a wideband cdma (wcdma) system. the rf output range needed is 1720 mhz to 1780 mhz. the vco190?750t will accomplish this. channel spacing is 200 khz with a 20 khz loop bandwidth. vco sensitivity is 32 mhz/v. charge pump current of 4.375 ma is used and the desired phase m argin for the loop is 45 . the if output is ?ed at 200 mhz. the vco190?00t is used. it has a sensitivity of 10 mhz/v. channel spacing and loop bandwidth is chosen to be the same as the rf side.
rev. 0 adf4206/adf4207/adf4208 C19C interfacing the adf4206/adf4207/adf4208 family has a simple spi- compatible serial interface for writing to the device. sclk, sdata, and le (latch enable) control the data transfer. when le goes high, the 22 bits that have been clocked into the input register on each rising edge of sclk will be transferred to the appropriate latch. see figure 1 for the timing diagram and table i for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible for the device is 909 khz or one update every 1.1 ms. this is certainly more than adequate for systems that will have typical lock times in hun- dreds of microseconds. aduc812 interface figure 10 shows the interface between the adf420x family and the aduc812 microconverter. since the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf420x family needs a 22-bit word. this is accomplished by writing three 8-bit bytes from the microconverter to the device. when the third byte has been written, the le input should be brought high to complete the transfer. on ?st applying power to the adf420x family, it requires four writes (one each to the r counter latch and the ab counter latch for both rf1 and rf2 side) for the output to become active. when operating in the mode described, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed will be about 180 khz. sclock mosi i/o ports aduc812 sclk sdata le muxout (lock detect) adf4206/ adf4207/ adf4208 figure 9. aduc812 to adf420x family interface adsp-2181 interface figure 10 shows the interface between the adf420x family and the adsp-21xx digital signal processor. as previously noted, the adf420x family needs a 22-bit serial word for each latch write. the easiest way to accomplish this using the adsp21-xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. set up the word length for eight bits and use three memory locations for each 22-bit word. to program each 22-bit latch, store the three 8-bit bytes, enable the autobuffered mode and then write to the transmit register of the dsp. this last opera- tion initiates the autobuffer transfer. sclock dt i/o flag adsp-21xx sclk sdata le muxout (lock detect) adf4206/ adf4207/ adf4208 tfs figure 10. adsp-21xx to adf420x family interface
rev. 0 C20C c01036C2.5C3/01 (0) printed in u.s.a. adf4206/adf4207/adf4208 outline dimensions dimensions shown in inches and (mm). thin shrink small outline package (tssop) (ru-16) 16 9 8 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.201 (5.10) 0.193 (4.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 thin shrink small outline package (tssop) (ru-20) 20 11 10 1 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.260 (6.60) 0.252 (6.40) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0

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